The present invention relates to a semiconductor device, and more particularly, to a semiconductor device, which is capable of exchanging data and a strobe signal with other devices in multiple I/O modes.
In order for high-speed data exchange between semiconductor chips, a strobe signal for strobing the data is used to correctly detect data. Accordingly, when exchanging data between the semiconductor chips at high speed, the semiconductor chips exchange the strobe signal as well as the data.
For example, when a synchronous dynamic random access memory (SDRAM), one of semiconductor memory devices, exchanges data (DQ) with a chipset (also called a memory controller), the SDRAM exchanges a data strobe signal (DQS) as well as the data.
FIG. 1 illustrates a clocking scheme to receive data DQ and a data strobe signal DQS in a receiver circuit of a semiconductor memory device (e.g., a double data rate (DDR) SDRAM).
The upper side of FIG. 1 illustrates the phase relationship between the data DQ and the data strobe signal DQS input from a chipset to the semiconductor memory device. As illustrated in FIG. 1, the data DQ and the data strobe signal DQS input from the chipset have a phase difference of 90 degrees. That is, the rising edges and falling edges of the data strobe signal DQS are aligned in the center of the data DQ.
Both the data DQ input to a data buffer 110 and the data strobe signal DQS input to a strobe input buffer 120 are output to a data detector 130. The data detector 130 may be implemented with a latch circuit. The data detector 130 latches the data DQ using the data strobe signal DQS aligned in the center of the data DQ to thereby allow the semiconductor memory device to correctly detect the data DQ.
Although not illustrated in FIG. 1, a delay line may be provided between the data buffer 110 and the data detector 130 or between the strobe input buffer 120 and the data detector 130 in order to compensate a delay difference caused by a physical distance between the data buffer 110 and the strobe input buffer 120 or a physical distance between a plurality of data buffers 110. Herein, the semiconductor memory device generally has eight data channels or sixteen data channels.
That is, a circuit for compensating a delay difference inevitably caused by a physical distance difference between a plurality of pins may be provided between the blocks illustrated in FIG. 1.
Since the compensation of the delay difference can be easily carried out by those skilled in the art, detailed description thereof will be omitted.
FIG. 2 illustrates a scheme to receive data DQ and a data strobe signal DQS in a receiver circuit of the chipset.
The upper side of FIG. 2 illustrates the phase relationship between the data DQ and the data strobe signal DQS input from the semiconductor memory device to the chipset. As illustrated in FIG. 2, the data DQ and the data strobe signal DQS input from the semiconductor memory device have with a phase difference of 0 degrees. That is, the rising edges and falling edges of the data strobe signal DQS are aligned in data boundaries between previous data and next data.
The data strobe signal DQS input to a strobe input buffer 220 of the chipset is input in a shifter 240. The shifter 240 shifts a phase of the data strobe signal DQS by 90 degrees. A data detector 230 latches the data DQ from data buffer 210 using the phase-shifted data strobe signal, whose rising and falling edges are aligned in the center of the data DQ, to thereby allow the chipset to correctly detect the data DQ.